Table 3 Comparison with previously proposed TRNG. The performances comparison of recent proposed TRNGs were fabricated on CMOS ASIC. It is difficult to compare the power consumption and the throughput fairly because the CMOS processes are different. In addition, the evaluations of randomness are different. Therefore, this shows state-of-the-art TRNGs for reference. We think that our TRNG is good balanced TRNG from the viewpoint of the power and the throughput
From: ASIC implementation of random number generators using SR latches and its evaluation
Entropy | Reference | Technology | Power | Throughput | Post processing | Random number evaluation |
|---|---|---|---|---|---|---|
Direct amplification | [8] | 0.18 μm | 3.6 mW | 5 Mbps | – | FIPS140-1, Knuth 2nd ed. |
Jitter oscillator sampling | [12] | 90 nm | 240 μW | 1.74 Mbps | LSFR | AIS31, Entopy dist. |
[13] | 65 nm | – | 7.5 Mbps | None | SP800-22Basic, DIEHARD | |
Metastable circuit | [18] | 0.13 μm | 1 mW | 40 Kbps | 5:1 decimation | SP800-22 Basic |
[19] | 0.35 μm | 9.4 μW | 5 Kbps | NSFR | SP800-22 Basic | |
[21] | 45 nm | 7 mW | 2.4 Gbps | – | SP800-22 | |
This work(MN) | 0.18 μm | 270 μW | 2.5 Mbps | – | SP800-90B, AIS20/31 | |
This work(ML) | 0.18 μm | 252 μW | 2.5 Mbps | – | SP800-90B, AIS20/31 |